In contemporary semiconductor device design practice there is a continued effort to increase the density of elements contained within the device while reducing the amplitude of the power supply voltage, increasing operational speed, and maintaining stable operation.
Semiconductor memory devices having multiple memory cell arrays accessed by a single input/output gate can not store logic high data into individual memory cells at the supply voltage level because of voltage drops associated with isolation transistors. That is, when storing data bits at logic high states, the exact power supply voltage level can not be precisely provided to the individual memory cells because clock signals applied to the gates of the isolation transistors only have voltages equal to the power supply voltage.
Therefore, the voltage provided to the individual memory cell array is decreased by the threshold voltage of the corresponding isolation transistor. One solution to this problem has been to boost the amplitude of the clock signals to levels exceeding the power supply voltage by at least the threshold voltage of the isolation transistors. Conventional boosting circuits however, tend to be inadequate in newer semiconductor memory devices. These devices generally operate at lower power supply voltages, e.g., 3.3 to 5 volts, and even at 1.5 volts. Although these new devices are more integrated requiring smaller transistors with reduced channel sizes and correspondingly lower threshold voltages, the drastically lower operating voltages tend to outweigh the beneficial effect of the lower threshold voltages. Furthermore, the boosting circuits operate less effectively at the lower supply voltages. Therefore, the art of boosting circuits must be advanced before further integration of the semiconductor memory devices can be be achieved.